The present invention relates to sense amplifier control, and more particularly, to a memory device sense amplifier control circuit for controlling a sensing start time of bit lines using a detected core voltage level, and a method for controlling the sense amplifier control circuit.
Generally, memory devices, such as a dynamic random access memory (DRAM), include memory cells each having a transistor and a capacitor. Data are stored in the capacitors of the memory cells. Each capacitor is formed on a semiconductor substrate but not completely isolated such that the capacitor is discharged (that is, data are not retained). In other words, data stored in the memory cells can be deleted due to current leakage. Therefore, the memory devices should be periodically refreshed so as to maintain charges of the capacitors.
In refresh mode, a memory device performs a refresh operation in response to an external command by sequentially accessing memory cells based on internal addresses. That is, when the memory device enters refresh mode in response to an external command, word lines of the memory cells are selected by periodically increasing low addresses in sequence. Charges stored in capacitors corresponding to the selected word line are amplified by a sense amplifier and are stored in the capacitors again. Owing to these refreshing procedures, data stored in the memory device can be retained.
Memory devices produce necessary internal voltages using an external power voltage having an upper voltage-level limit. In the case of a DRAM using a bit line sense amplifier, a core voltage VCORE is produced to amplify cell data. When a word line is active, data stored in a plurality of memory cells connected to the word line are transmitted to a bit line, and then the bit line sense amplifier senses and amplifies a voltage difference between a bit line pair.
As explained above, a voltage is applied to a bit line or an inverse bit line by a sense amplifier so as to charge capacitors of memory cells for storing data in the memory cells. The voltage is defined as a core voltage, and an internal driver generating the core voltage is called a core voltage driver. As DRAMs operate more rapidly, more rapid sensing is required, and thus the core voltage is required to be adjusted for rapid charging. Therefore, an overdriving method is used to disconnect the core voltage from an external power voltage VDD higher than the core voltage according to an operational current peak of a sense amplifier.
In other words, since several thousand bit line sense amplifiers operate simultaneously when a DRAM operates, the operational time of the bit line sense amplifiers is determined by whether a sufficient current is supplied to the bit line sense amplifiers. However, since the operational voltage of a memory device is low due to the low power consumption requirement, it is difficult to supply a sufficient current simultaneously. To address this, in an overdriving structure of a bit line sense amplifier, a high voltage greater than a normal voltage (generally, an internal core voltage) is momentarily supplied to a bit line sense amplifier power line RTO at an initial operation stage of the bit line sense amplifier (i.e., immediately after a bit line shares a charge with cells).
FIG. 1 is a block diagram of a conventional sense amplifier control circuit for a semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes a bank active delay unit 10, a precharge delay unit 12, and an active delay unit 14. The bank active delay unit 10 receives a bank active signal RACT and generates a signal RACTD after a predetermined time from the reception of the bank active signal RACT so as to control an active signal and a precharge signal. The precharge delay unit 12 generates a precharge delay signal PCG_P using the signal RACTD received from the bank active delay unit 10 so as to adjust a delay time in a precharge operation. The active delay unit 14 generates an active delay signal ACT_P using the signal RACTD received from the bank active delay unit 10 so as to adjust a delay time in an active operation.
The conventional sense amplifier control circuit includes a bit line sense amplifier control unit 16 and a sense amplifier driver 18. The bit line sense amplifier control unit 16 generates signals based on signals received from the precharge delay unit 12 and the active delay unit 14 so as to control overdriving or normal driving of a bit line sense amplifier. The sense amplifier driver 18 applies a driving voltage to bit line sense amplifier power lines RTO and SB in response to a signal received from the bit line sense amplifier control unit 16.
The conventional semiconductor memory device operates as follows.
When a control signal RACT providing bank active/precharge information is active, the bank active delay unit 10, the precharge delay unit 12, and the active delay unit 14 delay the control signal RACT for a predetermined time and generate an active delay signal ACT_P for an active operation interval and a precharge delay signal PCG_P for a precharge operation interval.
The bit line sense amplifier control unit 16 controls an operation of the bit line sense amplifier according to the active delay signal ACT_P and the precharge delay signal PCG_P generated by the bank active delay unit 10, the precharge delay unit 12, and the active delay unit 14.
That is, when an active signal is activated, the bit line sense amplifier is controlled to be in an active state (a signal SAN is in a high level). When the active delay signal ACT_P is input to the bit line sense amplifier control unit 16 by delaying the active signal for a predetermined time, the bit line sense amplifier control unit 16 activates an overdriving control signal SAP1 for a predetermined time.
While the overdriving control signal SAP1 is in an activated state, the sense amplifier driver 18 applies an external voltage to the bit line sense amplifier power line RTO (SB). Here, the external voltage has a potential level higher than that of a general core voltage. Therefore, data of memory cells connected to a pair of bit lines BL and BLb can be sensed and amplified more rapidly.
After a voltage level of the bit line pair become higher than a predetermined level, the bit line sense amplifier control unit 16 deactivates the overdriving control signal SAP1 and activates a normal driving control signal SAP2. Thus, a core voltage VCORE can be applied to the bit line sense amplifier power line RTO (SB).
Thereafter, if a precharge signal PCG is activated, the sense amplifier control circuit enables the bit line sense amplifier to be in a deactivated state (the signal SAN is in a low level). The precharge signal PCG is output from the precharge delay unit 12 as a precharge delay signal PCG_P after a predetermined delay time, and the precharge delay signal PCG_P is input to the bit line sense amplifier control unit 16. Then, the normal driving control signal SAP2 is deactivated in response to the precharge delay signal PCG_P.
In this way, during an active operation interval, the conventional sense amplifier control circuit performs a sensing operation by supplying a voltage to a bit line BL and an inverse bit line BLB of the bit line sense amplifier. Here, the sensing operation of the bit line sense amplifier is controlled based on the active delay signal ACT_P and the precharge delay signal PCG_P.
The active delay signal ACT_P and the precharge delay signal PCG_P are generated by delaying the signal RACT containing active/precharge information for a predetermined delay time. That is, the delay time for generating the active delay signal ACT_P and the precharge delay signal PCG_P is fixed.
Therefore, since the conventional sense amplifier control circuit generates the active delay signal ACT_P and the precharge delay signal PCG_P based on a fixed delay time, if the core voltage increases, the delay time can be insufficient, and thus a charging sharing interval of the bit lines BL and BLB can be short. In this case, sensing errors may occur.
That is, during an active operation interval, the conventional sense amplifier control circuit performs a sensing operation for applying high-level and low-level signals to a bit line and an inverse bit line of a bit line sense amplifier after a charge sharing interval during which a potential difference is caused by only cell data. During the charge sharing interval, a potential difference ΔV between the bit line and the inverse bit line is approximately 100 mV. Then, the sensing operation starts in response to a control signal (SAP1, SAP2).
However, if a core voltage level is increased higher than a normal level, a delay time before the sensing operation is shortened and thus a sufficient potential difference ΔV cannot be ensured. In spite of this situation, the sensing operation may start since the signal (SAP1, SAP2) is fixed, thereby increasing sensing errors.